NorthGuy Blog Archive
High Speed Digital Signals on Breadboard. Tests.
Posted by NorthGuy on Saturday, February 9, 2019 06:17 PM
While solderless breadboards are often considered unsuitable for prototyping high speed digital signals, our analysis[3] suggests that signals up to 200 MHz may be used in prototyping. We have conducted a series of experiments with real breadboards to test whether this conclusion is correct.

Methods

Tests were very simple. We used breadboardable FPGA module with Artix-7 FPGA[1]. One of the FPGA pins was used to produce a test signal while a different pin was used to capture the signal (Fig. 1). Since the FPGA module was mounted on breadboard, this automatically tests the breadboard performance.
Fig. 1. Test setup (see text for details)
We used several test patterns. Each pattern had duration of 20 ns. The pattern consisted of 16 intervals, each clocked by the edges of 400 MHz clock. By setting individual intervals to 0 or 1, we produced 12 different test patterns. Test patterns included square waves of various frequencies - 400 MHz, 200 MHz, 100MHz, and 50 MHz, as well as isolated high and low pulses of various duration - 1.25 ns, 2.5 ns, 3.75 ns, and 5 ns.
The test pattern was transmitted repeatedly, back to back, through the FPGA ODDR element clocked with 400 MHz clock. LVCMOS33 I/O-standard has been used with default drive strength of 12 mA and slew rate set to FAST.
The signal transmitted through the breadboard was captured by FPGA ISERDES element, which was clocked by the same 400 MHz clock which clocked the ODDR (see Fig. 1). Using the same clock to both generate the pattern and sample the results, ensured that the phase relationship between the sampling clock and the data being sampled was always the same. Therefore we could use equivalent time sampling - test different sampling points during different test cycles and then aggregate the results.
ISERDES provides 8 sampling points which occur on rising edges of the sampling clock and are spaced 2.5 ns apart covering the entire 20 ns period of the test pattern. To increase coverage, we used the IDELAY element (see Fig. 1), which can produce calibrated delays. The IDELAY has 32 taps which can generate any delay from 0 to 2.42 ns with 78 ps resolution. Configuring IDELAY for different taps allows sampling the signal at different points. Combining 32 taps with 8 clock edges generates 256 points spaced 78 ps from each other. This produces equivalent time sampling with effective resolution of 12.8 GSa/s, which should be more than enough for our purpose.
Fig. 2. Wires used in the test. Hereafter, the wires are referred to as "strap" (red), "short wire" (blue), and "long wire" (yellow)
We sampled each of 256 points 1000000 times. For most of the points, all 1000000 measurements were the same. However, for some points, samples were mixed - some of the samples were 0 while others were 1. We considered such points to be located in the jitter zone where the signal is transitioning form 0 to 1 (or from 1 to 0) and sampling a signal may return either value. For each experiment, we recorded the width of the received pulses as well as the width of the jitter zones around the pulse.
Fig. 3. Strap connection. The signal is transmitted from pin 48 of the FPGA board (breadboard strip 24) and received by pin 46 of the FPGA board (breadboard strip 22). Damping resistor shown.
Since the performance of breadboard circuits depends on the length of the wires being used[3], we have tested three different lengths of wire (Fig. 2) - short strap, which is barely long enough to connect two strips, short wire (approximately 7 inch (18 cm) long), and long wire - (approximately 14 inch (36 cm) long).
We run all the experiments with and without damping resistors. We have use through-hole components which are common in breadboard prototyping. The setup for the short wire is shown on Fig.3. Note how the strips around the wire are connected to the ground.
Fig. 4. Short wire connection. The signal is transmitted from pin 48 of the FPGA board (breadboard strip 24) and received by pin 26 of the FPGA board (breadboard strip 2). Damping resistor shown.
For longer wires (Fig. 4), we have located transmitting and receiving pins on the opposite sides of the FPGA. Both ends of the wire have been surrounded by the grounded strips.
Fig. 5. 74LVC8T245 buffer circuit assembled on breadboards. The signal is transmitted from pin 48 of the FPGA board (breadboard strip 24), processed through 74LVC8T245, and then received by pin 26 of the FPGA board (breadboard strip 2). Both damping resistors shown.
In addition to single wires, we also used a simple circuit which consisted of two different breadboards. The signal was routed through a level-shifter and buffer IC 74LVC8T245[2] and then back to the FPGA were it was captured (Fig. 5). The IC has been powered independently at 3.3V. The choice of IC may be not the best for the experiment, but it has been chosen simply because we had a breadboardable module with the IC.
In this circuit, there are two lines. One line goes from FPGA to the buffer IC. The other line goes from the buffer IC back to FPGA. For each of these lines, we have grounded the strips around the connection point, and also tried to use damping resistors on the receiving end.

Results

In some cases, it was impossible to distinguish any pattern in the data received - the data consisted of either all zeroes, or all ones, or all jitter. However, in most cases, we have observed clearly distinguishable pulses with narrow jitter zones between them.
The width of the jitter zone was typically one, rarely two taps (160 to 240 ps). This width was about the same in all cases. Therefore, we do not report it here.
The width of the pulses is clearly affected by the breadboard (Tables 1 and 2). In most cases pulses are elongated. The distortions are minimal for the short strap, but as the wire length increases, distortions become larger. Apparently, the elongation is caused by the inductance of the wire.
Short pulses couldn't make it through longer wires. 1.25 ns pulses could only be transmitted through a short strap. 2.5 ns pulses could be transmitted through longer wires, but was severely distorted. For example, high 2.5 ns pulse doubled in width when transmitted through the long wire (see Table 2).
Table 1. Distortion of isolated low pulses transmitted through breadboard. Each number represents average difference between the width of the received pulse and the width of the transmitted pulse (in ps). Negative numbers indicate pulses shortened in transmission, positive numbers indicate lengthened pulses.
Transmitted pulse width 1.25 ns 2.50 ns 3.75 ns 5.00 ns
Strap -508 -586 -313 -195
Strap with 220 Ω damping resistor -273 -273 +39 +39
Short wire   +1406 +1016 +977
Short wire with 220 Ω damping resistor   +1133 +859 +781
Long wire   +2188 +1797 +1484
Long wire with 220 Ω damping resistor   +820 +1016 +1250
Table 2. Distortion of isolated high pulses transmitted through breadboard. Each number represents average difference between the width of the received pulse and the width of the transmitted pulse (in ps). Negative numbers indicate pulses shortened in transmission, positive numbers indicate lengthened pulses.
Transmitted pulse width 1.25 ns 2.50 ns 3.75 ns 5.00 ns
Strap +39 -39 +195 +234
Strap with 220 Ω damping resistor -78 -195 -39 -78
Short wire   +1719 +1328 +1055
Short wire with 220 Ω damping resistor   +781 +586 +391
Long wire   +2578 +2109 +1563
Long wire with 220 Ω damping resistor   +586 +1016 +859
Use of the damping resistor improves the situation, especially for the long wires. Distortion diminishes, the pulses become less elongated. The effect is similar for both high and low pulses, however the influence of the damping resistor on high pulses (Table 2) is more pronounced than its influence on low pulses (Table 1). This is because the damping resistor not only damps oscillations, but also lowers the overall level of the signal (see [3]).
Let's now look at the transmission of square waves. The square wave consists of intermittent low and high pulses. Clearly, they cannot be both elongated at the same time. Therefore, if the square wave manages to pass through the breadboard, the distortions must diminish. And this is exactly what happens (Table 3).
Table 3. Duty cycle distortion of square waves transmitted through breadboard. Each number represents average difference between the width of the received high pulse and its nominal value (in ps). Positive numbers represent duty cycles above 50%. Negative numbers represent duty cycle below 50%.
Square wave frequency 400 MHz 200 MHz 100 MHz 50 MHz
Strap +391 +508 +234 +195
Strap with 220 Ω damping resistor 0 +117 -78 -39
Short wire     +156 -39
Short wire with 220 Ω damping resistor   -78 -156 -391
Long wire     +234 0
Long wire with 220 Ω damping resistor   -625 0 -313
For example, 100 MHz square wave consists of 5 ns pulses. When these pulses are transmitted through the breadboard they're elongated. Isolated high pulses transmitted through the long wire get elongated by 1563 ps (see Table 2). The low pulses get elongated by 1484 ps (see Table 1). However, when these pulses are combined together to form 100 MHz square wave, the magnitude of distortions diminishes to 234 ps (see Table 3).
Damping resistors may improve transmission of square waves. For example, 200 MHz square wave cannot make through long wires without damping resistors, but when a damping resistor is installed, it can.

Data Transmission

We have collected enough measurements to estimate at what speed serial data can be transmitted through the breadboard. We will do estimates for two-wire transmissions. One wire will be used as a clock, and the other wire will be used to transmit data. We will evaluate two methods: SDR and DDR.
SDR (Single Data Rate) is a data transmission scheme where the transmitter changes the data on the falling edge of the clock and the receiver samples the data on the rising edge of the clock (Fig. 6).
Fig. 6. SDR data transmission. Red arrows mark the points in time where the receiver samples the data.
The receiver has two timing requirements: it is necessary that valid data would be present for certain time prior to a sampling point (this time is called "setup") and also for certain time after the sampling point (called "hold", See Fig. 6). If the breadboard distorts the pulses to the extent where these requirements are not met, a reliable transmission is impossible.
Using our measurements, we can calculate the worst case. For example, if we want to estimate the worst scenario for setup margin for pulse D1 (see Fig.6) we must consider the case where the beginning of the D1 pulse has been delayed (by the amount of jitter), then the duration of the pulse has been distorted (according to data presented in Tables 1-3), then the end of the pulse has been further delayed because of the jitter. Meanwhile, the clock edge which clocks D2, might have arrived earlier because of the jitter. If, even in this worst case scenario, the transition between D1 and D2 happens earlier than the clock edge, the setup margin is positive, and the data transmission is possible. Otherwise, the setup time is negative, and the transmission fails.
The worst case for the hold margin will be opposite - the D1 pulse has started earlier, the width of the pulse has been distorted, the transition between D1 and D2 has also happened earlier because of the jitter, but the clock edge which samples D1 has been delayed. If, even in such situation, the transition between D1 and D2 happens later than the clock edge, the hold time is positive and transmission is possible.
DDR (Double Data Rate) is a data transmission scheme where the receiver samples data on every edge of the clock, both rising and falling(Fig. 7). DDR allows to transmit data twice as fast as SDR.
Fig. 7. DDR data transmission. Red arrows mark the points in time where the receiver samples the data.
The feasibility of DDR transmission may be evaluated using the same principles as in SDR case. However, DDR is also affected by the duty cycle distortion of the clock. This changes the time between sampling points and adversely affects both setup and hold margins.
To evaluate the possibility of the transmission at a given frequency and data rate, we have calculated setup and hold for all the pulses which might occur on the data line. For example, for 200 MHz SDR transmission, we used the following pulses: isolated high 5 ns pulse (from Table 2), isolated low 5 ns pulse (from Table 1), high and low pulses from 100 MHz and 50 MHz square waves (see Table 3). We have selected the worst setup of all these pulses, and the worst hold.
The calculated setup and hold margins for both SDR and DDR are listed in table 4.
Table 4. Estimated setup and hold margins for digital data transmissions on various breadboard connections (in ps). Positive numbers indicate that the connection is suitable for the communications at the given data rate, and corresponding cells are highlighted. Top number is the setup margin. Bottom number is the hold margin.
Clock frequency 400 MHz 200 MHz 100 MHz
Data rate DDR SDR DDR SDR DDR SDR
Strap -391
-273
+625
+742
+156
+273
+2148
+2344
+1953
+2148
+4688
+4883
Strap with 220 Ω damping resistor +352
+273
+977
+898
+898
+820
+2266
+2305
+2227
+2266
+4805
+4844
Short wire         +1328
+2227
+4805
+4844
Short wire with 220 Ω damping resistor     -469
+625
+1172
+1953
+1016
+1797
+4063
+4453
Long wire         +781
+2031
+4766
+4766
Long wire with 220 Ω damping resistor     -1328
-625
+547
+1797
+313
+1563
+4219
+4531
The results show that data transmission at 100 MHz (both DDR and SDR) is possible in all cases, even using the longer wires.
200 MHz is more problematic. DDR transmission is only possible through a short strap between adjacent breadboard strips. SDR transmission can be sustained through longer wires, but only if a damping resistor is used.
400 MHz is clearly too fast for the breadboard, however even DDR signal can be transmitted through the short strap with damping resistor. This is stunning. 400 MHz DDR signal produces 800 Mb/s data rate. It is really fast. For example, this is the maximum allowable rate for DDR2 SDRAM memory. It is very surprising that such data rates can be achieved on breadboards. Of course, this is not practical for prototyping.

Real circuit

The distortions exhibited by the 74LVC8T245 buffer circuit (see Fig. 5 above) were different from what we have seen with single wires. Single wires make both low and high pulses longer. In contrast, the buffer circuit elongates high pulses slightly, but shortens low ones (Table 5 and 6, see the "without damping resistors" row). The same distortion pattern can be seen for square waves: the high pulses are elongated, and low pulses shortened (Table 7).
Table 5. Distortion of isolated low pulses transmitted through 74LVC8T245 buffer circuit assembled on breadboards. Each number represents average difference between the width of the received pulse and the width of the transmitted pulse (in ps). Negative numbers indicate pulses shortened in transmission, positive numbers indicate lengthened pulses.
Transmitted pulse width 2.50 ns 3.75 ns 5.00 ns
Without damping resistors -391 -703 -430
With 220 Ω damping resistor at 74LVC8T245 -469 -625 -273
With 220 Ω damping resistor at FPGA +78 -78 +430
With 220 Ω damping resistors at both 74LVC8T245 and FPGA 0 0 +391
Table 6. Distortion of isolated high pulses transmitted through 74LVC8T245 buffer circuit assembled on breadboards. Each number represents average difference between the width of the received pulse and the width of the transmitted pulse (in ps). Negative numbers indicate pulses shortened in transmission, positive numbers indicate lengthened pulses.
Transmitted pulse width 2.50 ns 3.75 ns 5.00 ns
Without damping resistors +156 -79 +156
With 220 Ω damping resistor at 74LVC8T245 -78 -391 -117
With 220 Ω damping resistor at FPGA -469 -859 -625
With 220 Ω damping resistors at both 74LVC8T245 and FPGA -1016 -1094 -820
Table 7. Duty cycle distortion of square waves transmitted through 74LVC8T245 buffer circuit assembled on breadboards. Each number represents average difference between the width of the received high pulse and its nominal value (in ps). Positive numbers represent duty cycles above 50%. Negative numbers represent duty cycle below 50%.
Square wave frequency 200 MHz 100 MHz 50 MHz
Without damping resistors +234 +195 +234
With 220 Ω damping resistor at 74LVC8T245 +234 +313 +156
With 220 Ω damping resistor at FPGA -156 -508 -625
With 220 Ω damping resistors at both 74LVC8T245 and FPGA -156 -430 -625
It is impossible to determine the exact cause of the difference, but we may speculate that one of the factors is lower inductance of wires (the length of the wires is only about 4 inch (10 cm)). The capacitance of the 74LVC8T245 may play a role, as well as its slower slew rate.
Fig. 8. The distortion of the signal waveform may produce incorrect measurements of the pulse width. Such measurements may depend on the sampling voltage level.
When the inductance is low and capacitance is high, the shape of rectangular pulses is distorted similar to Fig. 8 (see [2]). When the receiver digitizes such signal, the pulse width becomes dependent on the location of the sampling threshold. Namely, if the sampling threshold is lower then high pulses become longer (7 ns vs 5 ns on Fig. 8) and, consequently, low pulses become shorter. This is exactly what we have observed with our circuit (see Tables 5 and 6).
Damping resistors do not improve the situation (see Tables 5 to 7). Wire inductance, which could have caused oscillations, is small. Therefore, there's nothing to damp. This makes damping resistors useless.
However, damping resistors decrease the amplitude of the signal (see examples in [2]). Any decrease in the amplitude also changes the position of the signal relative to the sampling threshold, and, consequently, the width of the pulses - high pulses should become longer, while low pulses should become shorter. We have observed this effect in our data. When a damping resistor was used at the FPGA, the width of low pulses had improved (see Table 5), but the high pulses had become shorter (see Table 6).
The overall effect of damping resistors is rather negative, especially if they're installed at the FPGA.
Table 8. Estimated setup and hold margins for digital data transmissions through 74LVC8T245 circuit assembled on breadboards (in ps). Positive numbers indicate that the connection is suitable for the communications at the given data rate, and corresponding cells are highlighted. Top number is the setup margin. Bottom number is the hold margin.
Clock frequency 200 MHz 100 MHz
Data rate DDR SDR DDR SDR
Without damping resistors +625
+156
+2109
+1641
+1953
+1484
+4570
+4336
With 220 Ω damping resistor at 74LVC8T245 +547
+234
+2031
+1875
+1719
+1563
+547
+234
With 220 Ω damping resistor at FPGA -313
+313
+1094
+1719
+625
+1250
+4688
+4531
With 220 Ω damping resistors at both 74LVC8T245 and FPGA -313
-78
+1094
+1328
+859
+1094
+3398
+4023
According to our estimates, the buffer circuit is good enough to transmit data at 100 or 200 MHz, both SDR and DDR (Table 8). Unlike single wires, the circuit works best without damping resistors.

Conclusions

High speed digital signals can pass through circuits built on breadboards. The signals are distorted, but distortions are manageable and often are below 500 ps. In fact, the distortions are so small that it would be impossible to detect them with a logic analyzer with sampling rate of 2 GSa/s or less.
Our study confirms that solderless breadboards are suitable for prototyping using 100 MHz digital signals. Prototyping at 200 MHz is also possible, but requires extra care to ensure signal integrity - wires must be as short as possible, damping resistors should be considered when necessary. Other important factors (such as EMI) which have not been included in this study must be considered as well. However, without any doubts, breadboards, and breadboardable modules can be used for high speed signals and can save time during prototyping.

References

 
Submit your comments on "High Speed Digital Signals on Breadboard. Tests.":
Name:
Email:
Security question: how do you call an electronic component which only conducts in one direction?
 

 

 

NorthGuy Blog Archive